Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL
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For a full description of the models, refer to the September 2007 MATLAB Digest article.
http://www.mathworks.com/company/newsletters/digest/2007/sept/sigmadelta.html
We present a series of Simulink models to design a high-level behavioral model of a Sigma-Delta ADC. The high-level behavioral model has an Analog section and a Digital section that comprises a digital filter. We partition the digital filter into three cascade filters that use a total of 10 times less filter coefficients than the original filter. We then elaborate the first filter in the cascade in such a way that it requires no multiplications for implementation. We convert our design to fixed-point. We then proceed to generate VHDL code for our elaborated filter using Simulink HDL coder. This is an example of Model-Based Design.
Citation pour cette source
Ali Behboodian (2024). Sigma-Delta ADC, From Behavioral Model to Verilog and VHDL (https://www.mathworks.com/matlabcentral/fileexchange/16416-sigma-delta-adc-from-behavioral-model-to-verilog-and-vhdl), MATLAB Central File Exchange. Récupéré le .
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- Code Generation >
- Code Generation > HDL Verifier >
- FPGA, ASIC, and SoC Development > HDL Verifier >
- FPGA, ASIC, and SoC Development >
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A inspiré : SIMULINK Sigma-Delta Toolbox
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1.0.0.0 | Added keywords |