Filter Design HDL Coder

Key Features

  • Generates synthesizable IEEE 1076 compliant VHDL code and IEEE 1364-2001 compliant Verilog code for implementing fixed-point filters in ASICs and FPGAs
  • Controls the content, optimization, and style of generated code
  • Provides options for speed vs. area tradeoffs and architecture exploration, including distributed arithmetic
  • Generates VHDL and Verilog test benches for quick verification and validation of generated HDL filter code
  • Generates simulation and synthesis scripts

The generated VHDL and Verilog code adheres to a clean HDL coding style that enables architects and designers to quickly customize the code if needed. The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation.

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