Simulink HDL Coder 1.7

Simulink® HDL Coder™  generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink® models, Stateflow® charts, and Embedded MATLAB™  code. The automatically generated HDL code is target independent.

The Simulink HDL Coder product generates Verilog code that complies with the IEEE 1364-2001 standard and VHDL code that complies with the IEEE 1076 standard. As a result, you can verify the automatically generated HDL code using popular functional verification products, including Cadence® Incisive®, Mentor Graphics® ModelSim®, and Synopsys® VCS®.  You can also map the automatically generated HDL code into field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) using popular synthesis tools, such as Altera® Quartus® II, Cadence Encounter® RTL Compiler, Mentor Graphics® Precision®, Synopsys Design Compiler®, Synplicity® Synplify®, and Xilinx® ISE™.

Simulink HDL Coder also generates HDL test benches that help you verify the generated HDL code using HDL simulation tools.