Learn how to use the Xilinx Targeted Design Platform for DSP to produce optimized FPGA implementations of algorithms modeled in MATLAB and Simulink.
This is the third of a three-part series on FPGA design using MATLAB and Simulink. In this webinar, we focus on use of System Generator for DSP, Xilinx’s tool that provides system modeling and automatic HDL code generation from Simulink® and MATLAB®.
Through discussion and demonstrations, Xilinx and MathWorks engineers will cover several topics.
- DSP capabilities of Virtex-6 and Spartan-6 FPGAs
- Xilinx DSP design flow, including Xilinx System Generator for DSP
- Integration of HDL generated from Simulink HDL Coder into designs created in System Generator
- Design validation and accelerated simulation in actual FPGA hardware using hardware cosimulation.
- Integration of System Generator into Xilinx RTL and embedded systems design flows.
About the Presenters:
Olivier Tremois is a DSP Specialist for Xilinx. Prior to joining Xilinx, Olivier earned a PhD in Digital Signal Processing at Rennes University in 1995 and then worked at Thalès Underwater Systems in the research department. After that he worked for four years as a DSP manager responsible for PHY layer research and development at a small firm involved in single-carrier and multicarrier telecommunication systems.
Stephan van Beek is a Signal Processing and Communications Engineer Application Engineer for MathWorks focused on FPGA implementation. Prior to joining MathWorks, Stephan worked at Anorad Europe BV as a field service engineer on motion control systems. After that he worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. Stephan studied electrical engineering at the Polytechnic in Eindhoven.
Enregistrés: 16 juin 2010